1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method of fabricating a semiconductor device. Although the present application is suitable for wide scope of applications, it is particularly suitable for forming a 1 GB DRAM or higher integrated semiconductor memory device.
2. Discussion of the Related Art
Development and research have been directed to DRAM devices capable of processing GB information in a chip. A dimension of a unit device to store a unit of information should be less than 0.3 .mu.m.sup.2 in a 1 GB DRAM device. Thus, a micro pattern-forming technique is generally required to realize a device having such a precise dimension. For example, a self-aligned contact hole method is one of the techniques for forming the micro patterns. Using this process, a unit cell having a dimension less than 0.3 .mu.m.sup.2 is readily achieved in forming micro patterns.
With the advent of the multi-media era, electronics have been developed which have improved and more complicated functions. In addition, the trend is towards smaller, lighter, and more portable systems. According to this trend, a multifunction semiconductor device built in one chip has received great attention. Particularly, a DRAM memory device region and logic device region tend to be built in one chip. To realize this design, processes of forming the memory device region and the logic device region should be performed at the same time, rather than separately.
A conventional method of fabricating a semiconductor device will be described with reference to the attached drawings.
FIGS. 1A through 1F are cross-sectional views showing the process steps of forming a memory device region of a DRAM cell, and FIGS. 2A through 2F are cross-sectional views showing the process steps of a method of forming a logic device region. In the conventional method, the memory device region and the logic device region are formed in separate processes.
Referring to FIG. 1A, after an active region and a field region are defined in a semiconductor substrate 1, a field oxide layer 2 is formed on the field region. Successively, a first oxide layer, a polysilicon layer, and a first silicon nitride layer (not shown) are formed on the entire surface of the substrate.
A photoresist film is coated thereon and selectively patterned by photolithography. With a photoresist pattern serving as a mask, the first silicon nitride layer, the polysilicon layer, and the first oxide layer are anisotropically etched to form a gate cap nitride layer 5, a gate line 4, and a gate oxide layer 3, respectively. N-type ions are then implanted into the substrate 1 to form a lightly doped drain (LDD) region 6 in the substrate 1.
As shown in FIG. 1B, a second silicon nitride layer 7 is deposited on the entire surface of the substrate including the gate cap nitride layer 5, the gate line 4 and the gate oxide layer 3.
Then, in FIG. 1C, the second silicon nitride layer 7 is anisotropically etched to form a sidewall insulating layer 7a at both sides of the gate oxide layer 3, the gate line 4, and the gate cap nitride layer 5. With the sidewall insulating layer 7a and the gate cap nitride layer 5 serving as masks, heavily doped n-type impurity ions are implanted into the substrate 1 to form a source/drain region 8.
As shown in FIG. 1D, a second oxide layer 9 is deposited on the substrate 1. Next, a photoresist film 10 is coated on the entire surface of the substrate and then patterned by photolithography to expose a portion of the second oxide layer 9, as shown in FIG. 1E.
Referring to FIG. 1F, with the photoresist film 10 serving as a mask, the portion of the second oxide layer 9 between the gate lines 4 is removed to expose the source/drain region 8 by a self-aligned contact hole process using different etch selectivities between the oxide layer and the silicon nitride layer.
A method of forming a logic device region having a silicide layer will now be described with reference to FIGS. 2A to 2F.
As shown in FIG. 2A, an active region and a field region are defined in a semiconductor substrate 11, and then a field oxide layer 12 is formed on the field region. Next, a first oxide layer and a polysilicon layer are deposited on the entire surface of the substrate. Then a photoresist film is coated and then partially patterned (not shown) by photolithography. With the photoresist pattern serving as a mask, the first oxide layer and the polysilicon layer are selectively removed to form a gate oxide layer 13 and a gate line 14 on the active region.
Referring to FIG. 2B, lightly doped n-type impurity ions are implanted into the substrate 11 to form an LDD region 15.
In FIG. 2C, a silicon nitride layer is deposited on the entire surface of the substrate including the LDD region 15, and then etched-back to form a sidewall insulting layer 16 on both sides of the gate oxide layer 13 and the gate line 14.
Subsequently, with the sidewall insulating layer 16 and the gate line 14 serving as masks, heavily doped n-type heavily doped impurity ions are implanted into the substrate 11 to form a source/drain region 17, as shown in FIG. 2D.
Referring to FIG. 2E, a metal layer 18 is deposited on the substrate 11. For example, titanium (Ti), cobalt (Co), or tantalum (Ta) may be used as the metal layer 18. Next, a silicide layer 19 in FIG. 2F is formed on the gate line 14 and the source/drain region 17 by annealing the metal layer 18. Thereafter, an unreacted portion of the metal layer 18 is removed from the silicide layer 19.
However, the conventional method of fabricating semiconductor devices have the following problems.
Since a sidewall insulating layer formed on both sides of the gate line in the cell region is formed of a silicon nitride layer, hot carriers are often trapped in the silicon nitride layer when a transistor is operated. Accordingly, the transistor tends to malfunction due to a high channel resistance. As a result, the device reliability is greatly lowered.
Further, a silicon nitride layer rather than an oxide layer is formed as a sidewall insulting layer in fabricating both the logic device region and the memory device region in the conventional method. Generally, the silicon nitride layer is more asymmetric than the oxide layer in crystallography. An eclectic force (for example, a Coulomb's force) dragging silicon atoms can be generated in the silicon nitride layer because of the asymmetry. Accordingly, silicon atoms in the source/drain region and the gate line move to the sidewall insulating layer in the silicon nitride layer, thereby forming a silicide in the sidewall layer. Consequently, a bridge electrically connecting the gate line and the source/drain region is formed and the semiconductor device can readily malfunction.